2024

• OpenNTT - An Automated Toolchain for Compiling High-Performance NTT Accelerators in FHE
  F. Krieger, F. Hirner, A. C. Mert, S. S. Roy,
  ACM/IEEE International Conference on Computer-Aided Design (ICCAD), 2024. (Preprint)

• Whipping the Multivariate-based MAYO Signature Scheme using Hardware Platforms
  F. Hirner, M. Streibl, F. Krieger, A. C. Mert, S. S. Roy,
  ACM Conference on Computer and Communications Security (CCS), 2024. (Preprint)

• Exploring the Advantages and Challenges of Fermat NTT in FHE Acceleration
  A. Kim, A. C. Mert, A. Mukherjee, Aikata, M. Deryabin, S. Kwon, H. Kang, S. S. Roy,
  Annual International Cryptology Conference (CRYPTO), 2024. (Link, Preprint)

• Proteus: A Pipelined NTT Architecture Generator
  F. Hirner, A. C. Mert, S. S. Roy,
  IEEE Transactions on Very Large Scale Integration (VLSI) Systems (Early access), 2024. (Link, Preprint, Code)

• Aloha-HE: A Low-Area Hardware Accelerator for Client-Side Operations in Homomorphic Encryption
  F. Krieger, F. Hirner, A. C. Mert, S. S. Roy,
  Design, Automation & Test in Europe Conference & Exhibition (DATE), Valencia, Spain, 2024. (Link, Preprint, Code)

• ModHE: Modular Homomorphic Encryption Using Module Lattices: Potentials and Limitations
  A. Mukherjee, Aikata, A. C. Mert, Y. Lee, S. Kwon, M. Deryabin, S. S. Roy,
  IACR Transactions on Cryptographic Hardware and Embedded Systems (TCHES), Issue 1, 2024. (Link, Code)

2023

• Efficient Design-Time Flexible Hardware Architecture for Accelerating Homomorphic Encryption
  E. Kocer, C. Ayduman, S. Kirbiyik, A. C. Mert, E. Savas,
  31st IFIP/IEEE Conference on Very Large Scale Integration (VLSI-SoC 2023), Sharjah, UAE, 2023. (Link)

• Parallel Hardware for Isogeny-based VDF: Attacker’s Perspective
  D. Jacquemin, A. Mukherjee, A. C. Mert, S. S. Roy,
  IACR Cryptology ePrint Archive, 2023. (Preprint)

• REED: Chiplet-Based Scalable Hardware Accelerator for Fully Homomorphic Encryption
  Aikata, A. C. Mert, S. Kwon, M. Deryabin, S. S. Roy,
  IACR Cryptology ePrint Archive, 2023. (Preprint)

• A Survey of Software Implementations for the Number Theoretic Transform
  A. C. Mert, F. Yaman, E. Karabulut, E. Ozturk, E. Savas, A. Aysu,
  International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), 2023. (Link)

• Kavach: Lightweight masking techniques for polynomial arithmetic in lattice-based cryptography
  Aikata, A. Basso, G. Cassiers, A. C. Mert, S. S. Roy,
  IACR Transactions on Cryptographic Hardware and Embedded Systems (TCHES), Issue 3, 2023. (Link, Code)

• Medha: Microcoded Hardware Accelerator for computing on Encrypted Data
  A. C. Mert, Aikata, S. Kwon, Y. Shin, D. Yoo, Y. Lee, S. S. Roy,
  IACR Transactions on Cryptographic Hardware and Embedded Systems (TCHES), Issue 1, 2023. (Link)

2022

• Exploring RNS for Isogeny-based Cryptography
  D. Jacquemin, A. C. Mert, S. S. Roy,
  IACR Cryptology ePrint Archive, 2022. (Preprint)

• KaLi: A Crystal for Post-Quantum Security
  A. Aikata, A. C. Mert, M. Imran, S. Pagliarini, S. S. Roy,
  IEEE Transactions on Circuits and Systems I: Regular Papers (Early access), 2022. (Link, Preprint)

• A Unified Cryptoprocessor for Lattice-based Signature and Key-exchange
  Aikata, A. C. Mert, D. Jacquemin, A. Das, D. Matthews, S. Ghosh, S. Sinha Roy,
  IEEE Transactions on Computers (Early access), 2022. (Link, Preprint)

• An Accelerated GPU Library for Homomorphic Encryption Operations of BFV Scheme
  E. R. Türkoğlu, A. Ş. Özcan, C. Ayduman, A. C. Mert, E. Öztürk, E. Savaş,
  IEEE International Symposium on Circuits and Systems (ISCAS), May 2022, Austin, US. (Link)

• CoHA-NTT: A Configurable Hardware Accelerator for NTT-based Polynomial Multiplication
  K. Derya, A. C. Mert, E. Ozturk, E. Savas,
  Microprocessors and Microsystems, vol. 89, Mar. 2022. (Link, Preprint, Code)

• Small MACs from Small Permutations
  M. Eichlseder, A. C. Mert, C. Rechberger, M. Schofnegger,
  IACR Cryptology ePrint Archive, 2022. (Preprint, Code)

2021

• Accelerator for Computing on Encrypted Data
  S. S. Roy, A. C. Mert, Aikata, S. Kwon, Y. Shin, D. Yoo,
  IACR Cryptology ePrint Archive, 2021. (Preprint)

• Efficient Number Theoretic Transform Implementation on GPU for Homomorphic Encryption
  O. Ozerk, C. Elgezen, A. C. Mert, E. Ozturk, E. Savas,
  The Journal of Supercomputing, 2021. (Link, Preprint, Code)

• A Hardware Accelerator for Polynomial Multiplication Operation of CRYSTALS-KYBER PQC Scheme
  F. Yaman, A. C. Mert, E. Ozturk, E. Savas,
  DATE Conference, Feb. 2021, Grenoble, France. (Link, Preprint, Code)

2020

• Low-Latency ASIC Algorithms of Modular Squaring of Large Integers for VDF Evaluation
  A. C. Mert, E. Ozturk, E. Savas,
  IEEE Transactions on Computers, 2020 (early access). (Link, Preprint)

• An Extensive Study of Flexible Design Methods for the Number Theoretic Transform
  A. C. Mert, E. Karabulut, E. Ozturk, E. Savas, A. Aysu,
  IEEE Transactions on Computers, 2020 (early access). (Link, Code)

• FPGA Implementation of a Run-time Configurable NTT-based Polynomial Multiplication Hardware
  A. C. Mert, E. Ozturk, E. Savas,
  Microprocessors and Microsystems, vol. 78, Aug. 2020. (Link)

• A Flexible and Scalable NTT Hardware: Applications from Homomorphically Encrypted Deep Learning to Post-Quantum Cryptography
  A. C. Mert, E. Karabulut, E. Ozturk, E. Savas, M. Becchi, A. Aysu,
  DATE Conference, Mar. 2020, Grenoble, France. (Link, Slides, Conference talk (25 min.))

• Design and Implementation of Encryption/Decryption Architectures for BFV Homomorphic Encryption Scheme
  A. C. Mert, E. Ozturk, E. Savas,
  IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 28, no. 2, Feb. 2020. (Link)

2019

• Design and Implementation of a Fast and Scalable NTT-Based Polynomial Multiplier Architecture
  A. C. Mert, E. Ozturk, E. Savas,
  Euromicro Conference on DSD, Aug. 2019, Kallithea, Greece. (Link, Preprint)

• Novel Approximate Absolute Difference Hardware
  A. C. Mert, H. Azgin, E. Kalali, I. Hamzaoglu,
  Euromicro Conference on DSD, Aug. 2019, Kallithea, Greece. (Link)

2018

• A Low Power Versatile Video Coding Fractional Interpolation Hardware
  A. C. Mert, E. Kalali, I. Hamzaoglu,
  Conference on DASIP, Oct. 2018, Porto, Portugal. (Link)

• A Reconfigurable Fractional Interpolation Hardware for VVC Motion Compensation
  A. C. Mert, H. Azgin, E. Kalali, I. Hamzaoglu,
  Euromicro Conference on DSD, Aug. 2018, Prague, Czech Republic. (Link)

• Efficient Multiple Constant Multiplication Using DSP Blocks in FPGA
  A. C. Mert, H. Azgin, E. Kalali, I. Hamzaoglu,
  International Conference on FPL, Aug. 2018, Dublin, Ireland. (Link, Code)

• An HEVC Fractional Interpolation Hardware Using Memory Based Constant Multiplication
  A. C. Mert, E. Kalali, I. Hamzaoglu,
  ICCE, Jan. 2018, Las Vegas, USA. (Link)

• An Efficient FPGA Implementation of HEVC Intra Prediction
  H. Azgin, A. C. Mert, E. Kalali, I. Hamzaoglu,
  ICCE, Jan. 2018, Las Vegas, USA. (Link)

2017

• Reconfigurable Intra Prediction Hardware for Future Video Coding
  H. Azgin, A. C. Mert, E. Kalali, I. Hamzaoglu,
  IEEE Transactions on Consumer Electronics, vol. 63, no. 4, Nov. 2017. (Link)

• An FPGA Implementation of Future Video Coding 2D Transform
  A. C. Mert, E. Kalali, I. Hamzaoglu,
  ICCE - Berlin, Sep. 2017, Berlin, Germany. (Link)

• Pixel Correlation Based Computation and Energy Reduction Techniques for HEVC Fractional Interpolation
  A. C. Mert, E. Kalali, I. Hamzaoglu,
  ICCE - Berlin, Sep. 2017, Berlin, Germany. (Link)

• High Performance 2D Transform Hardware for Future Video Coding
  A. C. Mert, E. Kalali, I. Hamzaoglu,
  IEEE Transactions on Consumer Electronics, vol. 63, no. 2, May 2017. (Link)

2016

• Low Complexity HEVC Sub-Pixel Motion Estimation Technique and Its Hardware Implementation
  A. C. Mert, E. Kalali, I. Hamzaoglu,
  ICCE - Berlin, Sep. 2016, Berlin, Germany. (Link)

• A Computation and Energy Reduction Technique for HEVC Discrete Cosine Transform
  E. Kalali, A. C. Mert, I. Hamzaoglu,
  IEEE Transactions on Consumer Electronics, vol. 62, no. 2, May 2016. (Link)

2015

• Development of an electronic control unit for PMSM drives in automotive applications
  B. Soner, A. Icke, A. C. Mert, U. Basaran, S. T. Impram, I. Sahin,
  ELECO, Nov. 2015, Bursa, Turkey. (Link)

Theses

• Efficient Hardware Implementations for Lattice-based Cryptography Primitives
  A. C. Mert, (Advisor: Dr. Erdinc Ozturk)
  Ph.D. Dissertation, Sabanci University, May 2021. (PDF)

• High Performance HEVC and FVC Video Compression Hardware Designs
  A. C. Mert, (Advisor: Dr. Ilker Hamzaoglu)
  MSc. Thesis, Sabanci University, August 2017. (PDF)

Patents

• Apparatus and method with homomorphic encryption
  A. Mukherjee, Aikata, A. C. Mert, Y. Lee, K. Sunmin, M. Deriabin, S. S. Roy,
  Patent Pub. No.: US 2024/0348421 A1, October 17, 2024. (Link)

• Apparatus and method with homomorphic encryption operation
  A. C. Mert, S. S. Roy, Aikata, S. Kwon, Y. Lee,
  Patent Pub. No.: US 2023/0327849 A1, October 12, 2023. (Link)

• Crypto processor and electronic device including the same
  S. S. Roy, A. C. Mert, Aikata, S. Kwon, Y. Shin, D. Yoo,
  Patent Pub. No.: US 2023/0132500 A1, May 4 2023. (Link)